As is known, MOS power devices have the need to form metal regions with low contact resistances on the front of the chip both on P-type regions (body regions) and on N-type regions (source regions). In fact, two of the fundamental characteristics for good operation of a MOS power transistor are the output resistance (Ron) and the direct voltage drop on the body-drain internal diode (Vf).
For a better understanding of the problems involved, reference may be made to FIG. 1, which illustrates a perspective cross-sectional view of a known MOS power transistor. In detail, the transistor is formed in a body 1 of semiconductor material comprising an N+-type substrate 2 and an N−-type epitaxial layer 3. P-type body regions 4 extend within the epitaxial layer 3 and house N+-type source regions 5. A rear metal region 7 extends on the back of the wafer, in contact with the substrate 2.
Gate regions 10, of polysilicon, extend on top of the body 1 and are electrically insulated from the latter by gate-oxide regions 11. The body regions 4 extend between adjacent gate regions 10, and two source regions 5 housed in two different body regions 4 extend along the edges of each gate region 10. Intermediate-dielectric regions 12 cover the gate regions 10 both at the top and at the sides. A source metal region 13, shown only partially for clarity, covers the surface of the body 1 and, on top of the body regions 4, electrically connects the body region 4 with the source regions 5 housed therein.
The portions of body regions 4 underneath the gate regions 10 (between each source region 5 and the edge of the body region 4 facing it) form channel regions 14.
To have low contact resistances, it is necessary to heavily dope both the N-type surface regions (source regions 5) and the P-type surface regions (body regions 4) in contact with the source metal region 13. The need for heavy doping of these regions gives, however, rise basically to two different problems.
A first problem is linked to the annealing processes subsequent to the implantation process and to their compatibility with the “scaled” thermal processes employed, for instance, in the manufacture of low-voltage submicrometric devices integrated in the same wafer.
The second problem is linked to the need to have low threshold voltages (1–2 V or even less) and hence low concentrations in the channel regions and, at the same time, high doping levels in the surface regions in contact with the metal regions.
In particular, in this regard, carrying out of an additional implantation for enrichment of the surface of the body regions 4 and of the source regions 5, through the windows in the polysilicon layer that forms the gate regions 10, would affect the surface concentration of the channel region 14 after the necessary annealing process. This has adverse effects on the threshold voltage, since both its mean value and the dispersion of its values would increase. In fact, the peak concentration in the channel region 14 is of the order of approximately 1017 atoms/cm3, while the surface concentrations in the contact area of the source 5 and body 4 regions must be higher than 1018 atoms/cm3, as may be seen from the plot of the doping profiles along the directions A and B, shown in FIGS. 1a and 1b, respectively.
The implantation dose further affects the defectiveness of the layers. In fact, as the dose increases, the likelihood of having precursor nuclei of extensive defects increases. On the other hand, these cannot be eliminated or in any case reduced to acceptable levels by using intensive thermal treatment, since this treatment could damage other parts or other devices integrated in the same chip.
In the above structure, the source regions 5 are obtained using an appropriate mask aligned inside the windows formed in the polysilicon layer. The above solution maximizes the channel perimeter (i.e., the facing perimeter between the source regions 5 and the channel regions 14) but may be used only when the distance between the gate regions is greater than 1 μm.
However, in case of structures of submicrometric size, the distance between the gate regions tends to be as small as possible, lower than 1 μm. For such devices, it is no longer possible to use the structure of FIG. 1, and the electrical connection between the source and body regions is obtained in two different ways.
For example, FIG. 2 (where L<1 μm) shows a solution wherein short-circuit is obtained through the use of an appropriate source mask. In practice, inside each body region 4, various source regions 5′ are formed, that, instead of extending in a continuous way along the edges of the gate regions 10, extend piece-wise in the direction Z for the entire width L (i.e., the width of the implantation windows of the body regions). In this way, body regions 4 have surface portions 4′, which face the top surface 6 of the body 1 and are electrically connected with the source regions 5′ through the metal layer 13. The above solution leads to a loss of channel perimeter even as much as 30% on account of the perimeter lost at the surface portions 4′. Furthermore, the problem of reducing the concentration of dopants in the source regions 5′ and hence of eliminating the problem of defectiveness is not solved.
A second solution, illustrated in FIG. 3, consists in carrying out an etch for partial removal of the source regions in the region facing the surface 6 of the body 1. In practice, in the above solution, the source regions are implanted in the polysilicon over the entire area of the windows. Then, after forming spacers 15 on the sides of the gate regions 10, the portions of the source regions not covered by the spacers 15 are removed for a depth greater that that of the source junction 5. At the end of the process, in each body region 4 just two thin source strips 5″ are present underneath the spacers 15, and the surface 6′ of the body 1 is no longer planar. In this case, etching of the silicon of the source regions 5 entails the need for contacting the source strips 5″ only along their vertical sides, with a considerable reduction in the contact area. Also in the above case, it is not possible to further reduce the defectiveness caused by the heavy doping of the source regions.
In all of the above cases, the source metal region 13 extends along the entire side edge of the gate regions 10 and is insulated from these by the side portions of the intermediate-dielectric regions 12 (see FIG. 1) or by the spacers 15 (see FIGS. 2 and 3). This facing area, hereinafter referred to as “insulation region”, is particularly critical and may be the cause of short-circuiting between the gate regions and the source regions on account of poor insulation. The insulation region plays an important role in the percentage of rejects since this percentage is proportional to the perimeter of the region, also referred to as “insulation perimeter”. The presence of a high insulation perimeter in known devices is therefore disadvantageous.
The aim of the invention is therefore to provide a MOS power device which will solve the problems outlined above.